Features

Mavalon is a CPU IP Core which can execute a subset of the MIPS 1 ISA. Its name is derived from the utilisation of the Avalon memory interface, which allows it to interface with memory-mapped devices such as RAM. Above all, Mavalon was built for reliability and simplicity to demonstrate how simple it can be to implement the MIPS ISA.

Below is a block-diagram of the final IP Core:

Additionally, Mavalon also has a comprehensive testing suite which can be used to test its correctness. This testing suite is agnostic of the underlying IP core, and could also be used to test correctness of other MIPS IP Cores.

Development

Mavalon was developed in a team of 5 for the Instruction Set Architectures & Compilers Course at Imperial College London - at the time, this part of the course was taught by Dr. David Thomas.

I was singularly responsible for the PC block, but also had significant contributions to the finite state machine (FSM), ALU and especially the the control block.

You can check out the Github repo for the project here.